This invention relates to clock control technology and, more particularly, to a clock control circuit and method using an interpolator for frequency multiplication.
In order to deal with an increase in the scale of circuitry that can be integrated on a single chip and in order to handle higher operating frequencies, semiconductor integrated circuits which include a synchronizing circuit that operates upon being supplied with a clock are provided with a clock control circuit for controlling phase and frequency of clocks externally and internally of the chip.
A PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop) is used conventionally as such a clock control circuit. In semiconductor circuits having system-scale circuitry on a single chip such as an LSI chip (referred to also as a xe2x80x9csystem on siliconxe2x80x9d), it is now necessary to provide a clock control circuit for phase and frequency control for each macroblock within the chip, by way of example.
In addition to use of a PLL or DLL as the conventional clock control circuit, as set forth above, it is also known to use a combination of a PLL or DLL and an interpolator.
FIG. 25 is a block diagram illustrating the structure of a clock control circuit, which comprises a combination of a PLL and an interpolator, described in Reference 1 (ISSC 1993 pp. 160-161, Mark Horowitz et al., xe2x80x9cPLL Design for a 500 MB/s Interfacexe2x80x9d). As shown in FIG. 25, a PLL 50 outputs multiphase clock signals P0 to Pn synchronized to an input clock 1. The multiphase clock signals P0 to Pn are input to a switch (selector) 20A. Two mutually adjacent signals (of even and odd phases) selected by the switch 20A enter an interpolator (a phase interpolator) 30A, which delivers an output signal OUT obtained by internally dividing the phase difference between these two input signals. The switch 20A that selects the pair of signals input to the interpolator 30A comprises an even-phase selector, a shift register for supplying a selection control signal to the even-phase selector, an odd-phase selector and a shift register for supplying a selection control signal to the odd-phase selector.
In the arrangement described in Reference 1, the interpolator 30A has an analog structure comprising a differential circuit that receives two inputs. A control circuit 40A has an FSM (Finite State Machine) circuit for monitoring phase to check which of the two signals is earlier in phase and for outputting a count signal to an up/down counter (not shown), and a DA converter (not shown) for converting the output of the up/down counter to an analog signal. The DA circuit supplies the interpolator 30A with a current corresponding to the even/odd phase. The PLL 50 comprises a phase comparator circuit, a loop filter, a voltage-controlled oscillator to which the voltage of the loop filter is input as the control voltage, and a frequency divider for frequency dividing the output of the voltage-controlled oscillator and feeding the resultant signal back to an input of the phase comparator circuit.
FIG. 26 is a block diagram illustrating an example of a clock control circuit, which comprises a combination of a DLL and an interpolator, described in Reference 2 (ISSCC 1997 pp. 332-333, S. Sidiropoulos and Mark Horowitz et al., xe2x80x9cA semi-digital delay locked loop with unlimited phase shift capability and 0.08-400 MHz operating rangexe2x80x9d). As shown in FIG. 26, a PLL 60 outputs multiphase clock signals P0 to Pn synchronized to the input clock 1. The multiphase clock signals P0 to Pn are input to a switch 20B. Two mutually adjacent signals enter an interpolator 30B, which delivers an output signal OUT obtained by internally dividing the phase difference between these two signals. On the basis of the result of detecting a phase difference between the output OUT and a reference clock, a control circuit 40B exercises control to vary the internal-division ratio of the interpolator 30B and controls the switching of the switch 20B. The interpolator 30B also is implemented by analog circuits.
FIG. 27 is a block diagram showing an arrangement described in Reference 3 (ISSCC 1997 pp. 238-239, Alan Fiedler, xe2x80x9cA 1.0625 Gb/s Transceiver with 2xc3x97-Oversampling and Transmit Signal Pre-Emphasisxe2x80x9d). This arrangement includes a voltage-controlled oscillator (VCO) 70 to which a clock is input for a adjusting the phase of multiphase clock signals, and a control circuit 40C. Multiphase clock signals Q0 to Qn are delivered from the output side of the VCO 70.
The clock control circuits according to the prior art described above have a number of problems described below.
In the implementation shown in FIG. 25 using the PLL, phase adjustment requires an extended period of time and jitter is produced by the feedback loop. The jitter causes a large shift in phase, which also occurs when the PLL is unlocked. In the implementations of FIG. 25 and 27, phase error occurs owing to a fluctuation in the center frequency of the VCO.
In the implementation shown in FIG. 26 using the DLL, there are occasions where the clock signal of the final phase of the multiphase clock signals develops a large shift. Loop jitter also occurs.
As shown in (b) of FIG. 13, with a DLL or the like, input-clock jitter (jitterxe2x88x92dt, which causes the clock period to become Txe2x80x94dt) appears in the last clock signal of the output clock (the cycle of the fourth clock pulse of a clock whose frequency has been multiplied by four is T/4xe2x88x92d). As a consequence, the influence of jitter is great.
Accordingly, an object of the present invention, in one aspect, is to provide a clock control circuit and method as well as a semiconductor integrated circuit device in which center-frequency fluctuation caused when a PLL is used and jitter due to a feedback loop are eliminated to thereby reduce phase error to a major degree.
Another object of the present invention is to provide a clock control circuit and method whereby multiphase clock signals can be generated in an instant.
According to a first aspect of the present invention, there is provided a clock control circuit comprising:
a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating a plurality of frequency-multiplied clocks, which have phases that differ from one another, from an input clock; and
at least one phase adjusting interpolator, to which are input two clocks from among the plurality of frequency-multiplied clocks of different phases output from the frequency multiplying interpolator, for outputting a signal obtained by internally dividing a phase difference between these two clocks.
According to a second aspect of the invention, there is provided a clock control circuit comprising:
(a) a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating multiphase clocks obtained by frequency multiplying an input clock;
(b) a switch, to which the multiphase clocks output from the frequency multiplying interpolator are input, for selectively outputting at least a pair of clocks from among the multiphase clocks;
(c) at least one phase adjusting interpolator, to which the pair of clocks output from the switch is input, for outputting a signal obtained by internally dividing a phase difference between the pair of clocks; and
(d) a control circuit for controlling a setting of an internal-division ratio of the phase adjusting interpolator and switching of a clock output by the switch.
According to a third aspect of the present invention, there is provided a clock control circuit comprising:
(a) a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating multiphase clocks obtained by frequency multiplying an input clock;
(b) one or a plurality of switches, to which the multiphase clocks output from the frequency multiplying interpolator are input, for outputting pairs of clocks of combinations selected from among the multiphase clocks;
(c) a plurality of phase adjusting interpolators, to respective ones of which the plurality of pairs of clocks selectively output from the switch are input, for outputting signals obtained by internally dividing a phase difference between each pair of clocks; and
(d) a control circuit for controlling a setting of an internal-division ratio of each of the phase adjusting interpolators and switching of a clock output by the switch.
According to a fourth aspect of the invention, there is provided an interpolator comprising:
a logic circuit, to which first and second input signals are applied, for outputting result of a predetermined logical operation between the first and second input signals;
a first switch element connected between a first power supply and an internal node and having an output signal of the logic circuit input to a control terminal thereof; and
a buffer circuit having an input terminal connected to the internal node for inverting an output logic value if a size relationship between potential of the internal node and a threshold value reverses;
a plurality of series circuits being connected in parallel between the internal node and a second power supply, each of the series circuits comprising a first constant-current source a second switch element turned on and off by the first input signal and a third switch element turned on and off by a control signal applied to a control terminal thereof;
a plurality of series circuits being connected in parallel between the internal node and the second power supply each of the series circuits comprising a second constant-current source, a fourth switch element turned on and off by the second input signal and a fifth switch element turned on and off by a control signal applied to a control terminal thereof;
a plurality of series circuits being connected in parallel between the internal node and the second power supply, each of the series circuits comprising a sixth switch element and a capacitor;
capacitance applied to the internal node being decided by turning on and off the sixth switch element by a cycle control signal applied to a control terminal thereof;
an output signal corresponding to a phase obtained by internally dividing a phase difference between the first input signal and the second input signal being delivered from the buffer circuit in dependence upon a combination of values of the control signals applied to the control terminals of the third switch elements and to the control terminals of the fifth switch elements.
According to a 5th aspect of the present invention, there is provided a clock control method comprising the steps of:
reducing jitter of a frequency-multiplied clock by generating multiphase clocks which are obtained by frequency multiplying an input clock, using a frequency multiplying interpolator which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals;
selecting two of the multiphase clocks, which are output from the frequency multiplying interpolator, by a switch and supplying the two clocks to a phase adjusting interpolator;
outputting from the phase adjusting interpolator a clock obtained by internally dividing a phase difference between the two clocks; and
performing control to vary an internal-division ratio of the phase adjusting interpolator based upon result of a phase comparison between a predetermined reference clock and an output clock of the phase adjusting interpolator.
According to a 6th aspect of the present invention, there is provided a clock control method using first, second and third interpolators each of which outputs a signal obtained by internally dividing a phase difference between two signals input thereto, the method comprising the steps of:
inputting a common data signal, which is transferred in sync with a clock signal to the first interpolator for delaying the data signal and then outputting the same;
inputting the clock signal to the second interpolator for outputting a clock signal obtained by internally dividing a timing difference between a leading edge and a trailing edge of a clock pulse;
inputting the clock signal to the third interpolator for outputting a clock signal obtained by internally dividing a timing difference between a trailing edge of the clock pulse and a leading edge of an ensuing clock pulse; and
latching data that is output from the first interpolator using a clock, which is obtained by multiplexing output signals from the second and third interpolators, as a latch timing pulse, and automatically adjusting latch timing to an optimum position with respect to the data independently of a fluctuation in duty of the clock signal.
According to a 7th aspect of the present invention, there provided a clock control circuit comprising:
a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;
a plurality of switches, to which the multiphase clocks output from the frequency multiplying interpolator are input for selecting and outputting pairs of clocks;
a plurality of interpolators, to respective ones of which the pairs of clocks output from the switch are input, for outputting signals obtained by internally dividing a phase difference between respective ones of the pairs of clocks; and
a control circuit for controlling a setting of an internal-division ratio of each of the interpolators and switching of a clock output by each of the switches;
a clock output from one of the interpolators being adjusted in phase so as to have a predetermined phase difference with respect to the input clock, and clocks output from the other of the interpolators being adjusted in phase so as to have a predetermined phase difference with respect to the input clock or with respect to an output clock of yet another interpolator.
According to a 8th aspect of the present invention, there is provided a clock control circuit comprising:
a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;
first and second switches, to which the multiphase clocks output from the frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;
a first interpolator, to which the pair of clocks output from the first switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;
a second interpolator, to which the pair of clocks output from the second switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;
a phase comparator circuit for detecting a phase difference between an output of the first interpolator and the input clock;
a filter for smoothing a signal representing the result of the phase comparison output from the phase comparator circuit;
a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the filter; and
a second counter, which is set to an offset value, for counting up and counting down based upon the signal representing the result of the phase comparison output from the filter;
setting of an internal-division ratio of the first interpolator and switching of a clock output by the first switch being performed based upon an output from the first counter; and
setting of an internal-division ratio of the second interpolator and switching of a clock output by the second switch being performed based upon an output from the second counter.
According to a 9th aspect of a clock control circuit comprising:
a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;
first and second switches, to which the multiphase clocks output from the frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;
a first interpolator, to which the pair of clocks output from the first switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;
a second interpolator, to which the pair of clocks output from the second switch is input, for outputting a clock signal obtained by internally dividing a phase difference between the pair of clocks and applying a phase adjustment;
the second interpolator having an output to which is connected a clock transmission path supplied with a clock;
the first interpolator having an output to which is connected a dummy circuit having a delay time equivalent to that of the clock transmission path;
a phase comparator circuit for detecting a phase difference between an output of the dummy circuit and the input clock;
a filter for smoothing a signal representing the result of the phase comparison output from the phase comparator circuit;
a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the filter;
a first decoder for decoding an output count from the first counter;
an adder circuit for adding the output count from the first counter and an input offset value; and
a second decoder for decoding an output from the adder circuit;
setting of an internal-division ratio of the first interpolator and switching of a clock output by the first switch being performed based upon an output from the first decoder; and
setting of an internal-division ratio of the second interpolator and switching of a clock output by the second switch being performed based upon an output from the second decoder.
According to a 10th aspect of the present invention, there is a clock control circuit comprising:
a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;
first, second and third switches, to which the multiphase clocks output from the frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;
first, second and third interpolators, to which the pairs of clocks output from the first, second and third switches, respectively, are input, for outputting clock signals obtained by internally dividing a phase difference between respective ones of the pairs of clocks and applying a phase adjustment;
the third interpolator having an output to which is connected a clock transmission path supplied with a clock;
a first phase comparator circuit for detecting a phase difference between an output of the first interpolator and the input clock;
a first filter for smoothing a signal representing the result of the phase comparison output from the first phase comparator circuit;
a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the first filter;
a first decoder for decoding an output count from the first counter;
an adder circuit for adding the output count from the first counter and an input offset value;
a second decoder for decoding an output from the adder circuit;
setting of an internal-division ratio of the first interpolator and switching of a clock output by the first switch being performed based upon a decoded output from the first decoder;
setting of an internal-division ratio of the second interpolator and switching of a clock output by the second switch being performed based upon a decoded output from the second decoder;
a second phase comparator circuit for detecting a phase difference between an output of the clock transmission path and the output of the second interpolator;
a second filter for smoothing a signal representing the result of the phase comparison output from the second phase comparator circuit;
a second counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the second filter; and
a third decoder for decoding an output count from the second counter;
setting of an internal-division ratio of the third interpolator and switching of a clock output by the third switch being performed based upon a decoded output from the third decoder.
According to a 11th aspect of the present invention, there is provided a clock control circuit comprising:
a multiphase clock generating circuit for generating and outputting multiphase clocks from an input clock or generating and outputting multiphase clocks by frequency multiplying the input clock;
first, second, third and fourth switches, to which the multiphase clocks output from the frequency multiplying interpolator are input, for selecting and outputting pairs of clocks;
first, second, third and fourth interpolators, to which the pairs of clocks output from the first, second, third and fourth switches, respectively, are input, for outputting clock signals obtained by internally dividing a phase difference between respective ones of the pairs of clocks and applying a phase adjustment;
the fourth interpolator having an output to which is connected a clock transmission path supplied with a clock;
a first phase comparator circuit for detecting a phase difference between the rising edge of an output of the first interpolator and the rising edge of the input clock;
a first filter for smoothing a signal representing the result of the phase comparison output from the first phase comparator circuit;
a first counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the first filter;
a second phase comparator circuit for detecting a phase difference between an output of the clock transmission path and the falling edge of a signal obtained by inverting the input clock by an inverting circuit;
a second filter for smoothing a signal representing the result of the phase comparison output from the second phase comparator circuit;
a second counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the second filter;
an averaging circuit for averaging an output count from the first counter and an output count of the second counter;
a first decoder for decoding an output from the first counter;
a second decoder for decoding an output from the second counter;
a third decoder for decoding an output from the averaging circuit;
setting of an internal-division ratio of each of the first to third interpolators and switching of a clock output by each of the first to third switches being performed based upon a decoded output from each of the first to third decoders;
a third phase comparator circuit for detecting a phase difference between an output of the clock transmission path and the output of the third interpolator;
a third filter for smoothing a signal representing the result of the phase comparison output from the third phase comparator circuit;
a third counter for counting up and counting down based upon the signal representing the result of the phase comparison output from the third filter; and
a fourth decoder for decoding an output count from the third counter;
setting of an internal-division ratio of the fourth interpolator and switching of a clock output by the fourth switch being performed based upon a decoded output from the fourth decoder.
According to a 12th aspect of the present invention, there is provided a clock control circuit comprising:
first, second and third interpolators each of which is for outputting a signal obtained by internally dividing a phase difference between two signals input thereto;
a common data signal being input to the first interpolator for being delayed and then output thereby;
a clock signal being input to the second interpolator, and the second interpolator outputting a clock signal obtained by internally dividing a timing difference between a leading edge and a trailing edge of a clock pulse;
the third interpolator outputting a clock signal obtained by internally dividing a timing difference between a trailing edge of the clock pulse and a leading edge of an ensuing clock pulse of the clock signal; and
a multiplexing circuit for multiplexing the output clocks from the second and third interpolators and outputting a clock signal;
the clock signal output from the multiplexing circuit being supplied to a latch circuit as a latch timing clock for latching data that is output from the first interpolator.
According to a 13th aspect of the present invention, there is provided a semiconductor integrated circuit device having a clock control circuit according to any one of the preceding aspects.
According to a 14th aspect of the present invention, there is provided a semiconductor integrated circuit device having a plurality of macroblocks, the device comprising:
a frequency multiplying interpolator, which includes a plurality of circuits each of which is for outputting a signal obtained by internally dividing a phase difference between two signals, for generating and outputting multiphase clocks obtained by frequency multiplying an input clock;
each of the macroblocks having a switch, to which the multiphase clocks output from the frequency multiplying interpolator are input, for outputting at least two clocks from among the multiphase clocks, and a phase adjusting interpolator, to which an output from the switch is input, for outputting a signal obtained by internally dividing the phase of the output; and
a control circuit for controlling switching of the clock by the switch and varying an internal-division ratio of the phase adjusting interpolator.
According to an embodiment, a clock control circuit comprises: a frequency multiplying interpolator including a plurality of circuits each for outputting a signal obtained by internally dividing the phase difference between two signals, the interpolator having an input clock applied thereto and outputting a plurality of clocks of different phases obtained by frequency multiplying the input clock; a switch to which the plurality of clock outputs from the frequency multiplying interpolator are input for switchingly (i.e., selectively) outputting two of the clocks; a phase adjusting interpolator to which the two outputs of the switch are input for outputting a signal obtained by internally dividing the phase difference between these two outputs; and a control circuit for controlling switching of the switch and for varying an internal-division ratio of the phase adjusting interpolator.
According to another embodiment a clock control circuit comprises: a frequency multiplying interpolator, which includes a plurality of circuits each for outputting a signal obtained by internally dividing a phase difference between two signals, for generating and outputting multiphase clocks obtained by frequency multiplying an input clock; a switch to which the multiphase clocks output from the frequency multiplying interpolator are input for outputting two of the multiphase clocks; a phase adjusting interpolator to which the two outputs of the switch are input for outputting a signal obtained by internally dividing the phase difference between these two outputs; and a control circuit for controlling switching of the switch and for varying an internal-division ratio of the phase adjusting interpolator.
According to a third embodiment, a clock control method comprises: reducing jitter of a frequency-multiplied clock by generating multiphase clocks, which are obtained by frequency multiplying an input clock, by a frequency multiplying interpolator, selecting two of the multiphase clocks, which are output from the frequency multiplying interpolator, by a switch and supplying the clocks to a phase adjusting interpolator; and varying an internal-division ratio of the phase adjusting interpolator based upon result of a phase comparison between a predetermined reference clock and output clocks of the phase adjusting interpolator.
Other aspects, features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.